1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming within microelectronics fabrications patterned layers of linewidth dimension narrower than the linewidth dimension of patterned photoresist layers employed in defining the patterned layers.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics fabrication technology has advanced, and microelectronics device and patterned microelectronics conductor layer density have increased, there has evolved a continuing and correlating trend towards decreasing linewidth dimensions of microelectronics devices and patterned microelectronics conductor layers through which are formed advanced microelectronics circuits within advanced microelectronics fabrications. The decreasing linewidth dimensions have typically traditionally been effected principally through decreasing the wavelength of photoexposure radiation employed in forming patterned photoresist layers which are employed in defining the linewidth dimensions of those microelectronics devices and patterned microelectronics conductor layers. Currently, photoexposure radiation is typically in the deep ultraviolet (DUV) (ie: 248 nanometer) wavelength region for forming microelectronics devices and patterned microelectronics layers of linewidth dimension typically as narrow as about 0.25 microns, while the most advanced photoexposure tooling typically employs a photoexposure radiation in the x-ray wavelength region for forming microelectronics devices and patterned microelectronics layers of linewidth dimensions in the deep sub-micron region as narrow as about 0.10 micron.
While the trend towards decreasing wavelength of photoexposure radiation as a means for providing microelectronics devices and patterned microelectronics layers of decreased linewidth dimensions within advanced microelectronics fabrications will most certainly continue, it nonetheless becomes important to provide methods and materials through which the evolution from the current generations of microelectronics fabrications having formed therein microelectronics devices and patterned microelectronics layers defined by photoexposure tooling employing a deep ultra-violet (NUV) (ie: 248 nanometer) photoexposure radiation wavelength to future generations of microelectronics fabrications having formed therein microelectronics devices and patterned microelectronics layers defined by advanced generations of photoexposure tooling employing an x-ray photoexposure radiation wavelength may be smoothly facilitated. In that regard, it is typically desirable to characterize to the extent possible, through relevant research and development activities, advanced microelectronics devices and patterned microelectronics layers of decreased linewidth dimensions at the earliest possible opportunity prior to committing production of microelectronics fabrications having formed therein those advanced microelectronics devices and patterned microelectronics layers of decreased linewidth dimensions to advanced photoexposure tooling. Among other advantages, such pre-production characterization allows for efficient use of advanced photoexposure tooling when initiating production of the advanced microelectronics fabrications within a manufacturing environment.
In particular, within advanced integrated circuit microelectronics fabrications having formed therein advanced field effect transistors (FETs) defined by gate electrodes of diminished linewidth dimensions, it is typically desirable to fully characterize those advanced field effect transistors (FETs) prior to production of those advanced field effect transistors (FETs) since the gate electrode linewidth within a field effect transistor (FET) defines the channel width within the field effect transistor (FET) which in part defines the operational characteristics of the field effect transistor (FET).
It is thus towards providing a method for forming within advanced microelectronics fabrications advanced microelectronics devices and patterned microelectronics layers having decreased linewidth dimensions without the need for employing advanced photoexposure apparatus in forming those advanced microelectronics devices and patterned microelectronics layers that the present invention is generally directed.
Various photolithographic methods, materials and apparatus have been disclosed in the art of microelectronics fabrication for forming patterned photoresist layers within microelectronics fabrications.
For example, Capari, in U.S. Pat. No. 4,625,120, discloses a deep ultraviolet (DUV) flood exposure apparatus for irradiating a deep ultraviolet (DUV) sensitive photoresist layer formed upon a microelectronics substrate such as a semiconductor substrate. The apparatus employs a xenon lamp positioned at the focal point of a spherical reflector which in turn is positioned at one end of a cylindrical baffle, where the sidewalls of the cylindrical baffle are fabricated such that the deep ultraviolet (DUV) sensitive photoresist layer formed upon the microelectronics substrate when positioned at the opposite end of the baffle is irradiated with a substantially collimated deep ultraviolet (DUV) radiation beam.
In addition, Premlatha et al., in U.S. Pat. No. 5,385,804, disclose a silicon containing negative photoresist material derived from a polysilsesquioxane polymer having incorporated therein aromatic azide side groups. The silicon containing negative photoresist material is developable within an aqueous alkaline developer, while simultaneously possessing enhanced oxygen plasma resistance and high sensitivity to deep ultraviolet, i-line and electron beam photoexposure radiation.
Further, Okamoto, in U.S. Pat. No. 5,641,715, discloses a photolithographic method employing either a chemical amplification positive electron beam photoresist material layer or a chemical amplification negative electron beam photoresist material layer for forming integrated circuit microelectronics structures within integrated circuit microelectronics fabrications. The photolithographic method employs a conductive polymer layer formed upon the chemical amplification positive electron beam photoresist material layer or the chemical amplification negative electron beam photoresist material layer, in order to prevent electrical charging of either of the chemical amplification photoresist material layers and to stabilize either of the chemical amplification photoresist material layers during an electron beam writing process.
Finally, Munzel et al., in U.S. Pat. No. 5,650,262, disclose a high resolution negative chemical amplification photoresist material developable with wide process latitude in an aqueous alkaline media. The high resolution negative chemical amplification photoresist material comprises: (1) a radiation sensitive acid generator; (2) a compound which reduces the solubility of the resist in aqueous alkaline media in the presence the acid; and (3) a polyhydroxy compound.
Desirable in the art of microelectronics fabrication are photolithographic methods through which there may be formed within advanced microelectronics fabrications microelectronics devices and patterned microelectronics layers having decreased linewidth dimensions without employing advanced photoexposure apparatus in forming those advanced microelectronics devices and patterned microelectronics layers. It is towards that goal that the present invention is directed.